1. Technical Field
The present invention relates to a system and method for verifying coherency between instruction cache and data cache. More particularly, the present invention relates to a system and method that test cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by test pattern branch instructions.
2. Description of the Related Art
A processor test team typically employs test patterns to verify and validate a system design. Processor testing tools exist whose goal is to generate the most stressful test pattern for a processor. In theory, the generated test pattern should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test patterns.
When an architecture permits an application to use the same memory page for both instructions and data, a possibility exists that a particular cache line may be pulled into both instruction cache (icache) and data cache (dcache). This is especially true when the application employs self-modifying code. As a result, maintaining coherency between icache and dcache is critical in order to ensure that updated instructions are picked for execution. In order to maintain coherency, snoop logic must detect changes in L1 cache lines and update other corresponding L1 cache lines accordingly. A challenge found, however, is that test applications use different cache lines for instructions and data even when they share the same page. As a result, existing art does not test situations when a particular cache line loads into both instruction cache and data cache.
What is needed, therefore, is a system and method that generates test patterns that test coherency between instruction cache and data cache.